It is quite common for new entrants into the world of verilog to get confused into vector and array. In simple terms a vector is a single element which could be 1 to n bit wide. For e.g.,
reg [7:0] temp; // where temp is vector of type reg and is 8 bit wide.
Note : while defining vectors index comes before identifier
Array as per definition in a collection of elements of same type. For e.g.,
int temp_array[11:0]; // an array of 12 elements of type int
Note : while declaring array, index comes after identifier
We can also declare an array of vectors. Let it be an 8 bit wide array of 4 bit vectors elements of type reg.
reg [3:0] temp_array_of_vectors[7:0];
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