What is a verilog test bench?

A verilog testbench is a module that instantiates a DUT (design module under test) and apply some stimulus to it as well as can have a mechanism to monitor and check output of DUT. A testbench usually have following template:

    module test_dut;

            // Declare Singals and Variables

            // Instantiate Design

            // Set initial value of stimulus

            // Apply stimulus

            // Observe Ouputs

            // Report pass/fail

     endmodule: test_dut