What is a module? How it is different from an instance?

A module is a basic building block in verilog. In encapsulates a collection of various lower level design blocks and primitive elements specified in verilog. It's functionality can be accessed through its ports but internal implementation is not visible. If module can be considered as template of design, instances are called actual design objects. So instances are the objects which can be created from templates called module. Each object has its own unique name, variable, parameters and I/O interfaces even though they are derived from same module. Instantiation is a process of creating objects from the module templates and objects are called instances.