What is the difference between intial and always blocks in verilog?

initial:
//sample code
      int cnt;      
      initial 
       begin
         cnt = cnt + 2;
         #20 cnt =  cnt  + 5;
         #20 cnt = cnt + 2;
      end

• initial block starts at simulation time 0 and all statement are executed once.
• execution of statement starts from begin and stops when the end of the block is reached.
• it cannot be synthesized.
  

always:
 //sample code
      reg [0:7] cnt;
      always (@negedge clk)
       begin
         cnt <= cnt + 2;
       end

• always block starts at simulation time 0 and repeats forever with changes in elements in sensitivity list.
• execution of statement starts from begin and stops only when wait statement in encountered.
• it is synthesizable construct of verilog.