When will you infer a latch in rtl design?

Take an example of if else statement, if we only mention output in if part but not in else part, in other words output is not assigned to any default value during the execution of always block in HDL it infers a latch.
e.g.,

always (select,input)
begin
if (select)
output <= input;
else;
end

or in case statement if either all cases are not mentioned or default statement in not included. Then we can infer a latch.
e.g.,

case (select_lines)
00: ;
01: ;
10: ;
endcase