What is the difference between intial and always blocks in verilog?

initial:
//sample code
      int cnt;      
      initial 
       begin
         cnt = cnt + 2;
         #20 cnt =  cnt  + 5;
         #20 cnt = cnt + 2;
      end

• initial block starts at simulation time 0 and all statement are executed once.
• execution of statement starts from begin and stops when the end of the block is reached.
• it cannot be synthesized.
  

always:
 //sample code
      reg [0:7] cnt;
      always (@negedge clk)
       begin
         cnt <= cnt + 2;
       end

• always block starts at simulation time 0 and repeats forever with changes in elements in sensitivity list.
• execution of statement starts from begin and stops only when wait statement in encountered.
• it is synthesizable construct of verilog.

What is a verilog test bench?

A verilog testbench is a module that instantiates a DUT (design module under test) and apply some stimulus to it as well as can have a mechanism to monitor and check output of DUT. A testbench usually have following template:

    module test_dut;

            // Declare Singals and Variables

            // Instantiate Design

            // Set initial value of stimulus

            // Apply stimulus

            // Observe Ouputs

            // Report pass/fail

     endmodule: test_dut

What is difference between $display and $monitor in verilog?

Both $display and $monitor in verilog are built in system task. Both enters a new line character at the end of displayed variable. Difference is however from the perspective of their invocation and duration. $monitor, once invoked keeps printing the variable continuously whenever there is change in the value of any of variable in the list. $display on the other prints the specified variables value only once and then terminates. To display value of listed variables at any other instant would need another invocation of $display task.
For e.g., let us take a variable temp that changes value at following instant
$Time : temp
10 : 3
20 : 7
30 : 9

Just one invocation of $monitor("temp = ",temp); would print
temp = 3
temp = 7
temp = 3

while we have to type $display at three place in the code to get the same result.

What is the difference between a vector an array in verilog?

It is quite common for new entrants into the world of verilog to get confused into vector and array. In simple terms a vector is a single element which could be 1 to n bit wide. For e.g.,

reg [7:0] temp; // where temp is vector of type reg and is 8 bit wide.
Note : while defining vectors index comes before identifier

Array as per definition in a collection of elements of same type. For e.g.,

int temp_array[11:0]; // an array of 12 elements of type int
Note : while declaring array, index comes after identifier

We can also declare an array of vectors. Let it be an 8 bit wide array of 4 bit vectors elements of type reg.
reg [3:0] temp_array_of_vectors[7:0];

What is sensitivity list?

Which will be Updated first ? Variable or signal?

Describe how blocking and non blocking statements get executed?

What is meant by inferring latches,how to avoid it?

What is difference between Verilog full case and parallel case?

Difference between $monitor,$display & $strobe?

What is delta simulation time?

Difference between inter statement and intra statement delay?

Write a verilog code to swap contents of two registers with and without a temporary register?

Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin
a = 0;
a <= 1;
$display(a);
end

What is code coverage and what are the different types of code coverage that one does ?